Define and drive the architecture of Biio's core compute engines — from ISA definitions and programming models through memory hierarchies and on-chip interconnects. Lead the overall chip architecture and tape-out program, own foundry and EDA relationships, and be the driving force behind the computational heart of our products, ensuring every cycle counts and every watt is well spent.
- Define and own compute engine architecture specifications, balancing performance, flexibility, power, area, and design complexity
- Lead architectural exploration from early concept through to specification, coordinating across modelling, implementation, verification, and physical design teams
- Specify execution units, memory hierarchy, instruction sets, and data flow — making principled trade-offs at every level
- Build and maintain performance models and simulators to guide architectural decisions with data
- Manage foundry and EDA relationships; prepare and evaluate end-to-end SoC designs for tapeout
- Evaluate emerging techniques — compact number formats, novel compute paradigms, advanced packaging — to inform the roadmap
- Act as a technical mentor, raising the bar for rigour in performance analysis and architectural documentation across the team
- Startup experience, or experience from one of the top organisations
- Degree in Electronic Engineering, Computer Science, Mathematics, Physics, or similar
- 10+ years of industry experience in processor or ASIC architecture, with at least 3 full tapeout cycles to your name
- Deep understanding of compute engine and processor architecture, including matrix/vector-centric floating-point arithmetic and memory hierarchies
- Strong grasp of RTL design flows and physical design constraints, and how they feed back into architectural choices
- Experience taking designs from early exploration through to tapeout and post-silicon performance characterization
- Background in AI acceleration, vector/matrix compute, or domain-specific processor design is highly desirable
- Excellent communicator who can bridge architectural depth with system- and product-level context
Work directly with the founders as a force multiplier — owning whatever needs owning to help a 10-person team move at the speed of a much larger one. One week that's fundraising support and investor materials, the next it's operations, hiring pipeline, customer research, or standing up an internal process from scratch. A high-trust, high-ambiguity role for someone who wants to see how a deep-tech company is built from the ground up.
- Be the founders' right hand — take ambiguous problems off their plate and drive them to done
- Support fundraising: investor research, data-room prep, deck iteration, and follow-ups
- Run operations and internal processes — set up the systems a growing team needs before it needs them
- Own the hiring pipeline end-to-end: sourcing, scheduling, candidate communication, and keeping the process moving
- Dig into customer and market research to sharpen positioning and go-to-market
- Jump into whatever is on fire that week — no task too big or too small
- Startup experience, or experience from one of the top organisations
- Exceptional generalist — organised, resourceful, and comfortable with ambiguity
- Bias for action: makes 80% decisions quickly and iterates
- Strong written and verbal communication; can represent the company to investors and customers
- No ego — will write docs, join customer calls, and do whatever the team needs
- Genuine interest in deep tech, hardware, or edge AI is a strong plus
Design the architecture and micro-architecture of an ultra-low-power ASIC on modern process technologies (≤ 28nm). Write SystemVerilog and code new tests to validate the design, do logic design and validation of custom IP, evaluate and integrate IP such as RISC-V, and prepare the end-to-end SoC design for silicon tapeout.
- Design and implement low-power techniques for RISC-V cores (clock gating, power gating, DVFS, multi-Vt, etc.)
- Implementation on FPGA
- Work across architecture, RTL, and physical design teams to integrate low-power features
- Perform power analysis, estimation, and optimization at block and system level
- Bring-up, debug, and test of the developed solutions on hardware
- You are passionate about low-power processor design and architecture
- Startup experience, or experience from one of the top organisations
- Degree in a technical subject — electronic engineering, computer science, mathematics, physics, or similar
- 5+ years of industry experience in low-power digital design, with focus on RISC-V or similar CPU architectures
- Solid knowledge of RTL design (SystemVerilog or Verilog) and power-aware simulation
- Experience with ultra-low-power designs
- Understanding of the RISC-V ISA and RISC-V power
Develop the machine learning compiler stack for Biio's AI acceleration hardware. Enable industry-leading performance of the latest AI models on Biio's accelerators, working with hardware and ML engineers in a highly collaborative hardware-software co-design methodology — directly shaping how intelligence runs at the edge.
- Build and optimize the end-to-end ML compiler stack targeting Biio's custom AI accelerators
- Map state-of-the-art neural network models onto novel compute architectures with maximum efficiency
- Develop and maintain compiler infrastructure using industry-standard technologies such as MLIR, LLVM, or TVM
- Drive performance analysis, profiling, and bottleneck resolution across the full software-hardware stack
- Work closely with hardware and architecture teams to feed software requirements back into silicon decisions
- You are passionate about the intersection of compiler technology, AI, and energy-efficient hardware
- Startup experience, or experience from one of the top organisations
- Degree in Computer Science, Electronic Engineering, Mathematics, Physics, or similar
- 3+ years of industry experience in compiler development, with focus on ML or hardware-targeting compilers
- Solid knowledge of C/C++ and hands-on experience with compiler frameworks such as LLVM
- Experience with machine learning compiler infrastructure (MLIR/IREE, TVM, or similar)
- Familiarity with polyhedral compilation techniques is a plus
- Creative and innovative mindset, with a willingness to take ownership in a fast-paced environment
Own the AI layer on both sides of Biio's operation: automate and accelerate the internal engineering workflows that let a 10-person team move at the speed of a much larger one, and build the model deployment pipelines that get neural networks running efficiently on Biio silicon. A dual-charter role — half productivity multiplier for the company, half technical contributor to the core product.
- Design and deploy internal AI workflows that eliminate repetitive overhead across engineering, documentation, simulation analysis, and customer communication — if a task is repeatable, it should be automated
- Build and maintain the end-to-end model deployment pipeline from PyTorch/ONNX through quantization, compression, and execution on Biio's edge AI architecture
- Work directly with the compiler and ASIC teams to validate model accuracy and power behaviour through the full INT4/INT8/INT16 quantization flow
- Develop tooling that makes it faster for OEM customers to evaluate Biio silicon — reducing the friction between a trained model and running inference on-device
- Identify and implement LLM-assisted workflows for code review, design documentation, test generation, and simulation result analysis
- Stay close to the bleeding edge of AI tooling — evaluate new models, agents, and frameworks with a ruthless focus on what actually saves time or ships faster
- Startup experience, or experience from one of the top organisations
- Degree in Computer Science, Electrical Engineering, or a related field
- 3+ years working across ML model deployment and/or AI-powered automation workflows
- Hands-on experience with model optimisation techniques: quantization, pruning, knowledge distillation, ONNX export
- Comfortable working across the stack — from Python scripting and CI/CD pipelines to understanding the hardware constraints that shape deployment decisions
- Experience building with LLM APIs, agent frameworks, or workflow automation tools (LangChain, n8n, or similar)
- A mindset that treats internal tooling as a product: if it isn't used, it doesn't count
- Familiarity with edge inference runtimes (TFLite, ONNX Runtime, or similar) is a strong plus
Work alongside our ASIC team on the physical implementation of an ultra-low-power chip on modern process technologies (≤ 28nm) — taking RTL through to a tapeout-ready layout. A hands-on internship for someone eager to learn the back-end flow on real silicon. Location-flexible.
- Support the physical design flow — floorplanning, placement, clock tree synthesis, and routing (place-and-route)
- Help run and analyse static timing analysis (STA) and close timing across corners
- Assist with power, area, and congestion optimization at block and top level
- Run physical verification checks (DRC / LVS) and help resolve violations
- Contribute to the end-to-end SoC design as it's prepared for silicon tapeout
- Learn low-power implementation techniques — clock gating, power gating, multi-Vt
- Working toward a degree in electronic engineering, computer science, or a related technical field
- Familiarity with digital design fundamentals and the ASIC back-end flow
- Exposure to EDA tools for place-and-route or timing analysis (e.g. Cadence, Synopsys) is a plus
- The right skills and attitude — bias for action, no ego, intrinsic drive
Support our ASIC engineers on the design architecture and micro-architecture of an ultra-low-power ASIC on modern process technologies (≤ 28nm). A hands-on internship for someone with the right skills and attitude, working on our proof of concept. Location-flexible — a chance to work on real silicon.
- Support ASIC engineers with design architecture and micro-architecture of an ultra-low-power ASIC on modern process nodes (≤ 28nm)
- Write SystemVerilog and code new tests to validate the design
- Logic design and validation of custom IP
- Evaluate and integrate IP such as RISC-V
- Prepare and evaluate the end-to-end SoC design for silicon tapeout
- Design and implement low-power techniques for RISC-V cores (clock gating, power gating, DVFS, multi-Vt, etc.)
- Working toward a degree in electronic engineering, computer science, or a related technical field
- Familiarity with SystemVerilog/Verilog and digital design fundamentals
- Exposure to RISC-V, FPGA prototyping, or low-power techniques is a plus
- The right skills and attitude — bias for action, no ego, intrinsic drive
Don't see your role but think you'd move the needle? We hire to solve a gap — make the case. careers@biio.ai